1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate chip-on-glass (COG) type array substrate of an LCD device.
2. Discussion of the Related Art
In general, an LCD device includes a liquid crystal panel having upper and lower substrates and a liquid crystal layer disposed between the upper and lower substrates, wherein peripheral portions of the upper and lower substrates are sealed together by a sealant to prevent leakage of the liquid crystal layer. The upper substrate, which is commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, which is commonly referred to as an array substrate, includes gate lines arranged along a transverse direction and data lines arranged along a longitudinal direction perpendicular to the gate lines. In addition, a pixel electrode is formed within a pixel region of the lower substrate defined by crossing regions of the gate and data lines, and a thin film transistor (TFT) is formed to function as a switching element at the crossing regions of the gate and data lines in a matrix. The TFT includes a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode contacts the pixel electrode via a drain contact hole. Accordingly, the gate lines transmit scanning signals to the gate electrode, and the data lines transmit data signals to the source electrode. Thus, the data signals change alignment of liquid crystal molecules of the liquid crystal layer according to the scanning signals in order to display images having various gray levels by the LCD device.
Operation of the LCD device makes use of optical anisotropy and polarization properties of the liquid crystal molecules in order to generate desired images. For example, the liquid crystal molecules have specific alignments due to their specific characteristics that can be modified by an induced electric field. Accordingly, since the electric fields induced to the liquid crystal molecules can change the specific alignments of the liquid crystal molecules, incident light is refracted according to the specific alignments of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules.
Each of the upper and lower substrates have electrodes that are spaced apart and face into each other. Accordingly, when the electric field is induced to the liquid crystal material through the electrodes of each substrate, alignment directions of the liquid crystal molecules are changed in accordance with the applied voltage to display images. By controlling the induced voltage, the LCD device provides various light transmittances to display images.
Among the different types of LCD devices, active matrix LCD (AM-LCD) devices having TFTs and pixel electrodes arranged in a matrix configuration produce high resolution images, and produce superior moving images. In the AM-LCD devices, driver integrated circuits (IC) apply signals to each electrode through a plurality of conductive lines disposed on the lower substrate, and may be mounted using various methods, such as chip on board (COB), tape carrier package (TCP), and chip on glass (COG) methods.
The COB method is commonly adopted for segment-type LCD devices, or for LCD panels having low resolution. Since the segment-type LCD devices or the low resolution LCD panels use small numbers of leads, the driver ICs thereof also have small numbers of leads. Accordingly, the driver ICs thereof are first installed on a printed circuit board (PCB) having a plurality of leads, and the leads of the PCB are connected with the LCD panel via one of the various methods described above. However, as resolution of LCD devices has increased, an increased number of leads are required for the driver ICs. Thus, when the number of leads increases, it is difficult to install the driver ICs on the PCB.
According to the TCP method, the driver ICs are installed onto a polymer film. Thus, the TCP method is commonly used for LCD devices that require small, thin, light weight packages, such as mobile phones.
According to the COG method, the driver ICs are directly installed onto the LCD panel without the use of an interposing PCB. Thus, electrical connections between the driver ICs and the LCD panel is miniaturized, wherein a pitch between adjacent leads of the driver ICs is relatively small. The COG method employs a multi-layered flexible printed circuit board (FPCB) instead of the PCB, wherein the multi-layered FPCB contacts the LCD panel via an anisotropic conductive film (ACF) and transmits input signals to the driver ICs.
Although the COG method has advantages, such as low cost and high stability, since a pad of the LCD panel requires an additional area to install the driver ICs, the LCD panel must be enlarged. In addition, by using the COG method, it is difficult to remove and repair defective ones of the driver ICs or to repair terminal lines of the LCD panel.
FIG. 1 is a schematic plan view of an LCD panel having a COG-type IC according to the related art, and FIG. 2 is a cross sectional view along II-II of FIG. 1 according to the related art. In FIGS. 1 and 2, a first substrate 10 is attached and aligned with a second substrate 50 such that the attached first and second substrates 10 and 50 constitute an LCD panel L.P. The first substrate 10 includes a plurality of gate and data pads (no shown) and IC chips 60 and 62 in electrical communication with the gate and data pads. The IC chips 60 and 62 are disposed along peripheries of the first substrate 10 that are not overlapped by the second substrate 50. Although not shown, the first substrate 10 includes a plurality of gate and data lines that perpendicularly cross one another to define a plurality of pixel regions, wherein the gate pad is disposed at each end of the gate lines, and the data pad is placed at each one end of the data lines. Specifically, the gate pads are located along the periphery where the gate driving IC chip 60 is placed such that the gate diving IC chip 60 is connected to the gate pads. Accordingly, the data pads are located along the periphery where the data driving IC chip 60 is placed such that the data driving IC chip 62 is connected to the data pads. In FIG. 2, a multi-layered flexible printed circuit board (FPCB) 70 is connected to the first substrate 10 through an anisotropic conductive film 80 to supply the driving signals to the driving IC ships 60 and 62.
FIG. 3 is a partially enlarged plan view of an array substrate according to the related art. In FIG. 3, an array substrate 10 includes a plurality of gate lines 14 disposed along a transverse direction and a plurality of data lines 28 disposed along a longitudinal direction, wherein the plurality of gate lines 14 and the plurality of data lines 28 cross one another to define pixel regions P. Each of the gate lines 14 and each of the data lines 28 include a gate pad 16 and a data pad 30, respectively, disposed at ends of each of the gate lines 14 and at ends of each of the data lines 28. In addition, a gate pad terminal 46 is disposed over the gate pad 16, and a data pad terminal 48 is disposed over the data pad 30. A TFT T is formed at each of the crossing portions of the gate lines 14 and the data lines 28, and may include a gate electrode 12, an active layer 20, a source electrode 24, and a drain electrode 26. A pixel electrode 44 may be disposed within the pixel region P defined by the gate and data lines 14 and 28, wherein the pixel electrode 44 and the gate and data pads terminals 46 and 48 are formed of a transparent conductive material. The cross-sectional structure of the aforementioned TFT and the gate and data pads will be explained in detail with reference to FIGS. 4-6.
FIG. 4 is a cross sectional view along IV-IV of FIG. 3 according to the related art, FIG. 5 is a cross sectional view along V-V of FIG. 3 according to the related art, and FIG. 6 is a cross sectional view along VI-VI of FIG. 3 according to the related art. In FIGS. 4-6, a switching region S, a pixel region P, a gate pad region G, and a data pad region D are defined on a substrate 10, wherein the gate electrode 12 is formed on the substrate 10 within the switching region S. As shown in FIG. 3, the gate line 14 is also disposed on the substrate 10, and the gate electrode 12 extends from the gate line 14. In FIG. 5, the gate pad 16 is formed on the substrate 10 within the gate pad region G, and is connected to the end of the gate line 14 (in FIG. 3). Then, a gate insulating layer 18, which is formed of an inorganic material, is formed on the substrate 10 covering the gate electrode 12, the gate line 14, and the gate pad 16. Next, an active later 20 is formed on the gate insulating layer 18, and an ohmic contact layer 22 is disposed on the active layer 20. Specifically, the active and ohmic contact layers 20 and 22 are disposed over the gate electrode 12, the source and drain electrodes 24 and 26 are disposed over the active layer 20 and are in contact with the ohmic contact layer 22, respectively. The data line 28 is disposed on the gate insulating layer 18, and the data pad 30 is also disposed on the gate insulating layer 18 within the data pad region D.
In FIG. 3, the data pad 30 is connected to the end of the data line 28. Accordingly, the TFT T including the gate electrode 12, the active layer 20, the ohmic contact layer 22, the source electrode 24, and the drain electrode 26 is formed over the substrate 10 within the switching region S, and the gate and data pads 16 and 30 are formed within the gate and data pad regions G and D, respectively.
Then, a first passivation layer 32 of an inorganic material is formed along an entire surface of the substrate 10 to cover the TFT T and the gate and data pads 16 and 30. Next, a second passivation layer 34 is disposed along an entire surface of the first passivation layer 32, and a third passivation layer 36 is disposed along an entire surface of the second passivation layer 34. The second passivation layer 34 is an organic material, while the first and third passivation layers 32 and 36 are an inorganic material. The organic material for the second passivation layer 34 may be, for example, benzocyclobutene (BCB) or acrylic resin, and the inorganic material for the first and third passivation layers 32 and 36 may be, for example, silicon nitride (SiNX) or silicon oxide (SiO2).
The first passivation layer 32 of inorganic material functions as a buffer layer to protect the active layer 20 from the passivation layer 34 formed of organic material. If the organic second passivation layer 36 contacts the active layer 20, a trap potential that interrupts carrier movement within a channel region of the TFT T may occur along an interface between the active layer 20 and the second passivation layer, thereby deteriorating operational characteristics of the TFT T. Therefore, the inorganic first passivation layer 32 is interposed between the TFT T and the organic second passivation layer 34.
Since the organic material for the second passivation layer 34 usually has a dielectric constant of less than 3, cross talk is prevented between the pixel electrode 44 and the lines 14 and 28. In addition, although the pixel electrode 44 extends over the gate and data lines 14 and 28, the second passivation layer 34 increases aperture ratio. When the organic material is utilized for the passivation layer, the aperture ratio is raised according to an extension of the pixel electrode 44. Accordingly, the third passivation layer 36 functions to interrupt light incident to the active layer 20.
After forming the third passivation layer 36 and before forming the pixel electrode 44, the first, second, and third passivation layers 32, 34, and 36 are simultaneously patterned to form first, second, and third contact holes H1, H2, and H3. The first contact hole H1 exposes a portion of the drain electrode 26, the second contact hole H2 exposes a portion of the gate pad 16, and the third contact hole H3 exposes a portion of the data pad 30. The second contact hole H2 penetrates the first, second, and third passivation layers 32, 34, and 36 and the gate insulating layer 18, whereas the first and second contact holes H1 and H3 penetrate only the first, second, and third passivation layers 32, 34, and 36.
After patterning the first, second, and third passivation layers 32, 34, and 36, the pixel electrode 44 is formed on the third passivation layer 36 to correspond to the pixel region P. Furthermore, when forming the pixel electrode 44, the gate and data pad terminals 46 and 48 are formed within the gate and data pad regions G and D, respectively. Accordingly, the pixel electrode 44 contacts the drain electrode 26 through the first contact hole H1, the gate pad terminal 46 contacts the gate pad 16 through the second contact hole H2, and the data pad terminal 48 contacts the data pad 30 through the third contact hole H3.
In FIGS. 3-6, the organic passivation layer is necessary in order to obtain the high aperture ratio. However, the structure causes some disadvantages within the gate and data pad regions G and D when installing the IC chips on the array substrate.
FIG. 7 is a cross sectional view along V-V of FIG. 3 of a gate pad region during application of an IC chip according to the related art. In FIG. 7, the first, second, and third passivation layers 32, 34 and 36 are simultaneously etched to form the second contact hole H2 that exposes the portion of the gate pad 16. However, during simultaneous etching of the first, second, and third passivation layers 32, 34, and 36, abnormal etching occurs due to the inorganic first and third passivation layers 32 and 36 and the organic second passivation layer 34 having different etching selectivities. For example, one of the organic and inorganic layers is over-etched during the patterning process such that the second hole H2 may have uneven surfaces along sidewalls of the second hole H2. Accordingly, the gate pad terminal 46 may be damaged, thereby creating an electrical open circuit condition. In addition, the electrical open circuit condition will be created within the data pad region D.
As a result, when the IC chip 60, having a bump 60a, is attached to the gate pad terminal 46 during the COG process, the IC chip 60 is electrically isolated from the gate pad 16. When the bump 60a of the IC chip 60 is larger than the second contact hole H2, the bump 60a is disposed on and in contact with the gate pad terminal 46. However, since the gate pad terminal 46 is damaged within the second contact hole H2, the gate pad terminal 46 does not electrically connect the gate pad 16 to the bump 60a of the IC chip 60, and the IC chip 60 is placed into an electrically floating state with respect to the gate pad 16. Thus, the IC chip 60 can not supply the signals to the gate pad 16.
FIG. 8 is a cross sectional view along V-V of FIG. 3 of another gate pad region during application of an IC chip according to the related art. In FIG. 8, since the bump 60a of the IC chip 60 has a relatively small size to fit within the second contact hole H2, the bump 60a impacts the gate pad terminal 46. Accordingly, the gate pad terminal 46 becomes detached from organic second passivation layer 34 and is damaged. Thus, the IC chip 60 is not electrically connected with the gate pad 16.
When the damage is created to the gate pad terminal 46, the IC chip 60 or the flexible printed circuit board (FPCB) 70 (in FIG. 2) is removed from the array substrate and a re-work process for re-attaching the IC chip 60 to the gate pad terminal 46 is performed. However, when removing the IC chip 60 or the FPCB 70 (in FIG. 2), the gate pad terminal 46 may be damaged such that a subsequent re-work process may not be performed since the gate pad terminal 46 is damaged beyond repair.